Certificate Programme in Digital VLSI Design
Programme by CEP, IIT Delhi
- Duration
6 Months
- Mode
Live Online Sessions via Direct to Device
- Session Timings
Sunday from 10:00 AM to 1:00 PM
Admission Criteria
Eligibility Criteria
- Any Electronics, Electrical, Physics or Computer Science Graduate.
- Candidates pursuing the graduation degree are also eligible however preference will be given to applicants with experience.
- Diploma holders (10 + 3) or (10 + 2 + 3) are also eligible.
Screening & Selection
- Screening and selection will be done by IIT Delhi.
Assessment
- 60% – End of programme MCQ-based exam
- 40% – Assignments & project
- 10% – Attendance (Grace)
- Candidates need to secure a minimum of 50% overall to be eligible for the certificate.
Attendance
- Minimum of 50% attendance is mandatory.
About IIT Delhi
Indian Institute of Technology Delhi is one of the Twenty-Three IITs created to be Centres of Excellence for Training, Research and Development in Science, Engineering and Technology in India. Established as College of Engineering in 1961, the Institute was later declared as an Institution of National Importance under the “Institutes of Technology (Amendment) Act, 1963” and was renamed as “Indian Institute of Technology Delhi”. It was then accorded the status of a Deemed University with powers to decide its own academic policy, to conduct its own examinations, and to award its own degrees.
Since its inception, over 48000 have graduated from IIT Delhi in various disciplines including engineering, physical sciences, management and humanities & social sciences of these, nearly 5070 received PhD Degrees. The number of students who graduated with B.Tech Degrees is over 15738. The rest obtained Master’s Degrees in engineering, sciences and business administration. These alumni today work as scientists, technologists, business managers and entrepreneurs. There are several alumni who have moved away from their original disciplines and have taken to administrative services, active politics or are with NGOs. In doing so, they have contributed significantly to building of this nation and to industrialisation around the world. For more details, please visit: www.iitd.ac.in.
- 2nd Rankas per NIRF India Engineering Rankings (2024)
- 2nd Rankas per QS World University Ranking (2024) in India
Pedagogical Methodology
Leaders
Learning Outcomes
Admission Process
- 1
Eligibility of Applicant
- 2
Application Submission
- 3
Screening & Shortlisting
- 4
Admission & Fee Payment
- 5
Book your Seat
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Syllabus Breakdown
- CMOS ASIC Design Flow
- The MOSFET Device
- The Interconnects
- The CMOS Inverter
- Inverter Delays and Power Dissipation
- The Combinational Logic Gates
- The Sequential Logic Gates
- Circuit Simulations using LTspice
- Digital Circuit Design Example
- Low-Power CMOS Circuit Design
- RTL Design using Verilog HDL
- RTL Verification and Finite State Machines (FSM)
- Capstone Project in Verilog Design & Synthesis
- Floor-Plan
- Placement
- Static Timing Analysis
- Clock Tree Synthesis and Signal Integrity
- Routing and DRC
- Layout Parasitic Extraction
- Advanced Floor planning and Placement Strategies
- Clock Tree Synthesis and Advanced Timing Analysis
- Signal Integrity and Electromigration Challenges
- Hardware architectures for AI/ML
- Neural network accelerator design
- Tensor processing unit fundamentals
- Hardware-software co-design for AI applications
- Optimization techniques for ML hardware
- Edge computing architectures
- Security hardware implementation
- AI based VLSI Design (CAD)
- Post Silicon Chip Validation
- Chip Integration and Packaging
- Introduction to 3D IC Design and Chiplet Architectures
- Automotive IC design considerations
- IoT chip design
- 5G/6G communication hardware
- UNIX Environment
- Basic Linux Commands
- Shell-Scripting
- Introduction to PERL Programming
- PERL Programming
- Argument Parsing, Loops and Functions
- File Handling
- Regular Expressions in PERL
- 24 hours of Lab module is planned in the programme.
- Labs will be conducted online. Various projects and hands-on training will be provided during lab hours.
- Circuit Simulation Tool: LTSpice
- Verilog Simulation Tool: ModelSim
- FPGA/RTL Design Tool: Xilinx Vivaldo
- FPGA Development Tool: Quartus Prime Lite
- Operating System and Languages: Linux/Tcl
Some of the projects planned are given below:
- Project 1: Combinational and Sequential CMOS Circuit Design
- Project 2: CMOS Low Power I/O Circuit Design
- Project 3: Power Management IC (PMIC) Design
- Project 4: Clock Tree Synthesis and Static Timing Analysis
- Project 5: Design for Test (DFT) and Automatic Test Pattern Generation (ATPG)
Programme Fee Details
- Easy EMI Options Available*
- *Payment of fees should be submitted in the IIT Delhi CEP account only and the receipt will be issued by the IIT Delhi CEP account for your records.
- *Loan Options is a service offered by Jaro Education. IIT Delhi is not responsible for the same.
Total Programme Fee
INR 1,20,000/- + GSTInstalment Pattern
Instalment 1
INR 80,000/- +GST (3 days from date of offer)Instalment 2
INR 40,000/- + GST (On or before 15th July 2025)Earn a Career Certificate
- Candidates who score at least 50% marks overall and have a minimum attendance of 50% will receive a ‘Certificate of Completion’ from CEP, IIT Delhi.
- Participants who are unable to score 50% marks in the evaluation but maintain a minimum attendance of 50% will be eligible for the ‘Participation Certificate’ from CEP, IIT Delhi.
- The above e-certificate is for illustrative purposes only and the format of the certificate may be changed at the discretion of IIT Delhi.
- Only e-certificate will be provided and it will be issued by CEP, IIT Delhi.
- The organizing department of this programme is the Centre for Applied Research in Electronics (CARE) at IIT Delhi.
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- Career Acceleration: Get unmatched career guidance, resume-building workshops, and 1:1 mentorship to fast-track your professional growth.
- 24/7 Student Support: Dedicated assistance at every step—from enrollment to graduation.
- Future-Ready Learning: Engage in immersive, industry-aligned programs designed for lifelong career relevance.
Expert-Led Doubt Resolution
- Learn from the Best: Access mentorship from top-tier faculty and industry leaders.
- Collaborative Learning: Join dynamic discussion forums and peer-to-peer networks for deeper insights.
- Real-World Problem Solving: Apply knowledge through case studies and interactive sessions.
Powerful Global Networking
- Elite Alumni Community: Connect with 350,000+ professionals worldwide for career opportunities and collaborations.
- Exclusive Events: Attend global webinars, networking meetups, and industry talks.
- Lifelong Access: Stay updated with cutting-edge trends and alumni benefits long after graduation.
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Start Referring Today! Start Referring Today!Frequently Asked Questions
- This programme in Digital VLSI Design offers hands-on exposure to industry-standard tools and methodologies, along with practical design projects and case studies, which enhance problem-solving capabilities and readiness to tackle real-world design challenges.
- Participants will gain exposure to industry-standard tools such as CAD tools, hardware description languages (HDLs), simulation tools, and scripting languages like Shell, Tcl, Perl, and Python. They will also learn about design synthesis, DFT, scan, ATPG, and other essential methodologies in digital VLSI design.
- The lab module consists of 24 hours of online sessions where participants engage in hands-on projects and training related to digital VLSI design. Various projects, including Combinational and Sequential CMOS Circuit Design, Power Management IC Design, and Clock Tree Synthesis, are planned to provide practical experience.
Following are some of the ideal career prospects
- Digital VLSI Design Engineers: Participants can embark on careers involving the design and development of digital integrated circuits, focusing on optimizing performance and efficiency.
- ASIC Designers: Learners can pursue roles specializing in Application-Specific Integrated Circuit (ASIC) design, tailoring circuits to specific applications or functionalities.
- Verification Engineers: Opportunities exist in verification engineering, where participants ensure the functionality and correctness of digital designs through rigorous testing and validation processes.
- Academic Research: Those inclined towards academia can engage in further research in digital VLSI design, contributing to advancements in the field through innovative research projects and publications.
Potential career paths include VLSI Designer, VLSI Test Engineer, Digital System Analyst, and IC Verification Engineer. The job market for individuals with Digital VLSI Design skills is promising, with increasing demand due to technology advancements. Moreover, opportunities in academia, research, and development are also available for experts in this field.
- The total programme fee is INR 1,20,000/- + GST. Interested individuals are encouraged to connect with Jaro Education’s admission experts for more information on the enrollment procedure.
